Verilog Lhs in Procedural Continuous Assignment May Not Be a Net

foreword

What is an assignment statement? That is to put the value on the wire net or variable, this operation is called assignment, English: assignment.
It has three basic forms:

• procedural assignment
• continuous assignment
• Process continuous assignment

text

reasonable lvalue

An assignment statement has two parts - right value (RHS) and left value (LHS), with an equal sign (=) or a less than equal sign (< =) in the middle
As you will see in the next blog post, = assigns blocking values and < = assigns non blocking values

In procedural assignment, a reasonable lvalue would be:

• variable (vector/scalar)
• Bit selection or partial selection of vector reg, integer, or time variables.
• Memory (Memory word)
• a merger of any of the above

Procedural assignments usually occur in block statements, such as initial blocks, always blocks, and task s and function s.

In continuous assignment, a reasonable lvalue should be:

• wire mesh (vector/scalar)
• Bit selection or partial selection of vector wire meshes.
• Combination of bit selection and partial selection

Consecutive assignments usually occur in assign.

Process continuity assignment:

• net or variable (vector/scalar)
• Bit selection or partial selection of net vectors

RHS can contain any expression that evaluates to a final value, while LHS represents a net or a variable to which the value in RHS is assigned.
E.g:

module tb; 	reg clk; 	reg a, b, c, d, e; 	wire f, y; 	reg  z;  	// clk is on the LHS and the not of clk forms RHS 	always #10 clk = ~clk;  	// y is the LHS and the constant 1 is RHS 	assign y = 1;  	// f is the LHS, and the expression of a,b,d,e forms the RHS 	assign f = (a | b) ^ (d & e);  	always @ (posedge clk) begin 		// z is the LHS, and the expression of a,b,c,d forms the RHS 		z <= a + b + c + d; 	end  	initial begin 		// Variable names on the left form LHS while 0 is RHS 		a <= 0; b <= 0; c <= 0; d <= 0; e <= 0; 		clk <= 0; 	end endmodule          

Procedural assignment

Procedural assignments occur in procedures, such as always, initial, task, and functions, to place values ​​on variables. The variable will hold that value until the next assignment to the same variable.

When the simulation executes the statement at some point in simulation time, the value will be placed on the variable. This can be controlled and modified the way we want by using control flow statements such as if-else-if, case statements and looping mechanisms.

reg [7:0]  data; integer    count; real       period;  initial begin 	data = 8'h3e; 	period = 4.23; 	count = 0; end  always @ (posedge clk) 	count <= count + 1;          

variable declaration assignment

An initial value can be placed on a variable when it is declared, as shown in the following figure. This assignment has no duration and holds the value until the next assignment to the same variable occurs.

Note that assignment of variable declarations to arrays is not allowed.

module my_block; 	reg [31:0] data = 32'hdead_cafe;  	initial begin 		#20  data = 32'h1234_5678;    // data will have dead_cafe from time 0 to time 20 		                              // At time 20, data will get 12345678 	end endmodule          

reg [3:0] a = 4'b4;  // is equivalent to  reg [3:0] a; initial a = 4'b4;          

If the variable is initialized at time 0 during declaration and in the initial block, as in the example below, the assignment order is not guaranteed, so the variable value can have 8'h05 or 8'hee.

module my_block; 	reg [7:0]  addr = 8'h05;  	initial 		addr = 8'hee; endmodule          

This method is not recommended, and normal people will not do this.

reg [3:0] array [3:0] = 0;           // illegal integer i = 0, j;                    // declares two integers i,j and i is assigned 0 real r2 = 4.5, r3 = 8;               // declares two real numbers r2,r3 and are assigned 4.5, 8 resp. time startTime = 40;                 // declares time variable with initial value 40          

continuous assignment

This is used to assign values ​​to scalar nets and vector nets, which happens whenever the RHS changes. It provides a way to model combinatorial logic without specifying the interconnection of gates and makes it easier to drive nets with logic expressions.

// Example model of an AND gate wire  a, b, c;  assign a = b & c;          

Whenever the value of b or c changes, the entire expression in the RHS will be evaluated and a will be updated with the new value.

Note: we can still make continuous assignments in line declarations, for example:

wire  penable = 1;          

But we have to use it with caution, because a net can only be declared once, so a net can only have one declaration assignment.

That is to say, once we perform continuous assignment when declaring the wire variable, we cannot assign it continuously again later, otherwise it will be multiple drivers.

Process continuity assignment

This assignment type seems to be rarely heard, but it exists.
There are two types:

• assign ... deassign
• force ... release

assign ... deassign

This overrides all procedural assignments to the variable and deactivates by using the same signal as deassign. The value of the variable will remain the same until the variable acquires a new value through procedural or procedural continuous assignment. The LHS of an assignment statement cannot be a bit selection, partial selection, or array reference, but can be a variable or a concatenation of variables.

reg q;  initial begin 	assign q = 0; 	#10 deassign q; end          

For testing, I simulated it, the simulation file:

module assign_tb();  reg q;  initial begin     assign q = 0;     #10 deassign q;          #10 q = 1;          #10 $finish;      end  endmodule          

According to the grammar description, the first 20ns should be kept as 0 for assign, and then 1;

The simulation results show the same.

force...release

These statements are similar to assign… deassign statements, but can also be applied to nets and variables. LHS can be a bit select of a net, a partial selection of a net, a variable or a net, but not a reference to an array and a bit/part selection of a variable. The force statement will overwrite all other assignments to the variable until it is freed using the release keyword.

reg o, a, b;  initial begin 	force o = a & b; 	... 	release o; end          

For testing, we design the following simulation files:

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer:reborn lee // Create Date: 2020/07/18 17:36:02 // Module Name: assign_tb //////////////////////////////////////////////////////////////////////////////////  module assign_tb();  reg o, a = 1, b = 1;  initial begin      force o = a & b;          #10 a = 0;     b = 0;     o = 1;          #10 a = 1;     b = 1;     o = 0;               #20 release o;            #10      a = 1;     b = 1;     o = 0;          #10      a = 0;     b = 1;     o = 1;      #10 $finish;      end  endmodule          

Now analyze this simple test program:
At the beginning, since the initial values ​​of a and b are both 1, and:

            force o = a & b;          

Therefore, the value of o is 1;
After 10ns, the values ​​of a and b are assigned 0, so o should be 0, but at the moment:

// force o = a & b;          #10 a = 0;     b = 0;     o = 1;          

We try to pull o high;
Also after 10ns:

//initial begin    //  force o = a & b;          //#10 a = 0;     //b = 0;     //o = 1;          #10 a = 1;     b = 1;     o = 0;          

We try to pull o low again;
It can be seen from the following simulation diagram that all are successful.

This shows that, before release, all operations on the variable o are ignored.

Continue to see, after release, our operations on o are all successful:

past review

Verilog Beginner Tutorial (13) Block Statements in Verilog

Verilog Beginner Tutorial (12) generate block in Verilog

Verilog Beginner Tutorial (11) initial block in Verilog

Verilog Beginner Tutorial (10) Verilog's always block

Verilog Beginner Tutorial (9) Verilog Operators

Verilog Beginner Tutorial (8) assign statement in Verilog

Verilog Beginner Tutorial (7) Verilog Module Instantiation and Handling of Dangling Ports

Verilog Beginner Tutorial (6) Verilog Modules and Ports

Verilog Beginner Tutorial (5) Multidimensional Arrays and Memory in Verilog

Verilog Beginner Tutorial (4) Scalar and Vector in Verilog

Verilog Beginner Tutorial (3) Verilog Data Types

Verilog Beginner Tutorial (2) Beginner Grammar of Verilog HDL

Verilog Beginner Tutorial (1) Know Verilog HDL

Chip Design Abstraction Layer and Its Design Style

Code guidelines advocated by Verilog and VHDL

Should FPGA/ASIC beginners learn Verilog or VHDL?

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Source: https://array.pub/a/verilog-beginner-tutorial-14-assignment-statements-in-verilog.html

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